Field of the Disclosure
Embodiments of the present disclosure generally relate to data and memory storage systems, and more particularly, to a memory device utilizing a three-dimensional Network-on-Chip routing protocol for the interconnection of memory subarrays, mats, arrays, subbanks, and/or banks.
Description of the Related Art
The cerebral cortex of a computer is a magnetic recording device, which typically may include a rotating magnetic media or a solid state volatile or non-volatile media device. A number of different technologies exist today for storing information for use in a computing system.
In recent years, there has been a demand for higher density devices—volatile and non-volatile—which maintain a relatively low cost per bit, for use in high capacity storage applications. Today the memory technologies that generally dominate the computing industry are DRAM and NAND flash; however, these memory technologies may not be able to address the current and future capacity or energy demands of next generation computing systems.
Existing non-volatile memory bank architecture employs a classic fabric routing methodology, which has been widely adopted in SRAM, DRAM, FLASH, MRAM, PCM, and ReRAM, as well as with HMC memory banks HMC memory banks utilize Through-Silicon-Via (TSV) to interconnect stacked dies with a Network-on-Chip-like protocol to access the many dies. However, each die is a classic DRAM die based on traditional H-Tree routing techniques to route the many subarrays. This classic methodology limits the density and amount of memory cells that may be included in a single die as well as the amount of bandwidth and access points to the same memory bank.
Traditionally, memory banks are architectured and organized as banks comprising arrays of subbanks. Each subbank may comprise multiple MATs. Each MAT may be composed of four or more subarrays and predecoding logic. As such, H-Tree routing may be used to route the I/O of the subarrays across the die vertically and horizontally. However, approximately 60% to 80% of the area is utilized to interconnect the subarrays; therefore, the majority of the surface of the memory is logic interconnection and not memory. As such, the biggest limitation with existing memory bank architecture is the amount of wire necessary to route the entire memory. Excessive amount of wire is the main cause for latency in existing memory banks from SRAM to DRAM. Given the physical limitations of traditional memory banks, subarrays share wordlines to write and read. As such, each bank can only access one subarray at a given time. With such limitations, there may only be one physical access interface, due to complexity and cost, to implement additional interfaces.
Hence, there is a need in art for an improved memory device that utilizes an improved three-dimensional routing protocol, allowing for access to any given subarray in parallel while improving total density and bandwidth. Furthermore, there is a need in the art for an improved three-dimensional apparatus and method for routing memory banks without employing a majority of the die for routing.